Every infringement read, the product it lands on, and how strong it is — across the AI chip market.
40
chip & IP designers (the map)
700+
named infringers in total, incl. §271 use
8
Axis patents in play
View 1 · The map
The chip & IP designers.
The companies whose own silicon or IP performs a patented method — charted directly against a claim, then placed by how defensible the read is (left → right) and the size of the accused market (bottom → top). Color marks the patent; a solid ring is a literal match, dashed is doctrine of equivalents. Everyone downstream who runs these chips is in View 5. Hover any company.
Not our characterization — the accused products’ own developer docs, instruction sets and architecture manuals describe the patented mechanism. (Several defendants patented it too — a willfulness hook you’ll see in the hovers.)
“cuStreamWaitValue blocks work until the memory condition is satisfied; cuStreamWriteValue writes the value.”
NVIDIA · CUDA Driver API → Axis ’565036
“CP_WAIT_REG_EQ waits until a register equals a reference value; CP_EVENT_WRITE then advances it.”
“each AI Engine stream-switch port can be routed in circuit-switched or packet-switched mode.”
AMD · Versal AI Engine manual → Axis ’811387
“a package of chiplets — each a grid of compute tiles, each tile pairing a control CPU with its compute slices.”
d-Matrix · Corsair · Hot Chips 2024 → Axis ’075768
View 3 · By patent
Reads across the portfolio.
Three patents read completely on shipping silicon; five more carry narrowed-claim reads held as leverage.
View 4 · Market scale
Size of the accused base.
Relative scale of the accused products in the U.S. — installed base and shipment volume. Not a damages model.
View 5 · Every read
Companies, products & reads.
Company
Accused products
Patent
Read
Validity
Forum
View 6 · The wider field
Everyone downstream.
The same US 10,565,036 method as the chip designers in the map — one step downstream. These parties don’t design the silicon; they embed it in finished products, ship the runtimes that perform the method, or operate it at scale. Because ’036 covers the dispatch every GPU performs, this field is open-ended — representative names by category, each tagged by how it infringes. Hover any name.
Representative, not exhaustive. Direct product defendants appear in the map above; the names here add the device & system OEMs whose products embed the accused silicon, the framework/runtime publishers that induce the method (§271(b)), and the operators that practice it in the U.S. by use (§271(a)). Federal systems carry a §1498 government-contractor posture.
View 7 · Element by element
The claim chart.
For litigators: the lead read and a non-fit, charted against the same patent and the same claim construction — US 9,075,768, claim 1. Each limitation is mapped to the accused instrumentality with a primary-source citation. Both turn on the same dispositive limitation — the self-similar-recursion element [1f–g] the patent was allowed on. (Click either die image to enlarge.)
Corsair compute chiplet (Hot Chips 2024): four identical quads, each repeating Slice 0–3 — a grid-of-grids.
Construction: a “computing plane” = an independently self-controlled processing core (a control plane + an associated datapath of the same logical architecture at every level). Patentee lexicography, claim 1[a] / spec [0008].
Every limitation met → literal infringement of claim 1 (dependent 2, 5, 6 follow).Proven largely by d-Matrix’s own granted patents — a defendant cannot disclaim its own sworn IP.
Element
Claim limitation
Accused feature & source
Met
1[pre]
A multi-core processor
16 compute chiplets, all-to-all connectedd-Matrix US 12,386,774
✓
1[a]
A plurality of cores (“computing planes”)
Each Quad holds 4 Slices; each Slice = DIMC + SIMD coresCorsair whitepaper
✓
1[c]
Each plane = a control plane + an associated datapath
Each Quad pairs a RISC-V control core + Dispatch Engine with its Slices’ computeCorsair whitepaper · US 12,260,223
✓
1[d]
Sequencing instruction memory within the control plane
The RISC-V control core + Dispatch Engine hold the per-Quad instruction sequenceCorsair whitepaper
✓
1[e]
Datapath of compute / storage / interconnect elements
DIMC + SIMD cores (compute); Data Reshape Engine (interconnect)Corsair whitepaper
✓
1[f]–[g]Dispositive
Self-similar recursion — an element above the lowest level is itself a complete lower-level plane
Package → chiplet → quad → slice: each higher unit’s compute is performed by complete lower-level control-plane + datapath units of the same designd-Matrix US 12,260,223 / 12,386,774 · Hot Chips 2024
✓
1[b]/[h]
A hierarchy of ≥2 levels of computing planes
package → chiplet → quad → sliceHot Chips 2024 die
✓
Colossus Mk2 die (Hot Chips 2021): a uniform array of identical tiles in columns joined by the Exchange — wiring, not nested processors.
Graphcore IPU
GC200 “Colossus Mk2” / Bow · 1,472 tiles
US 9,075,768 · Claim 1 · Does not infringe
Construction: same — a “computing plane” is a complete self-controlled core (control plane + datapath) that recurs at each level. An interconnect grouping of cores is not a plane.
Fails the self-similar-recursion limitation [1f–g] — the sole basis of allowance.One missing dispositive limitation = no infringement, literal or under doctrine of equivalents. Examiner’s Statement of Reasons for Allowance.
Element
Claim limitation
Accused feature & source
Met
1[pre]
A multi-core processor
A 1,472-tile IPUGraphcore, Hot Chips 33
✓
1[a]
A plurality of cores
The 1,472 IPU tilesGraphcore, Hot Chips 33 (“1,472 processor tiles”)
✓
1[c]
Each core = a control plane + a datapath
Each tile has independent control + execution (true MIMD)Citadel “Dissecting the IPU” (arXiv 1912.03413)
✓arguendo
1[d]
Sequencing instruction memory in the control plane
Per-tile local instruction memoryCitadel report
✓arguendo
1[e]
Datapath of compute / storage / interconnect elements
Tile compute units + local SRAMGraphcore, Hot Chips 33
✓arguendo
1[f]–[g]Dispositive
Self-similar recursion — an element above the lowest level is itself a complete lower-level plane
Tiles are grouped into islands of 4, then columns — but these are Exchange-wiring / proximity groupings, not computing planes. A tile is not built from smaller tiles, and an island/column does not repeat the tile’s control-plane + datapath design.Citadel report · Graphcore Hot Chips 33 (“Exchange spine 1600×36b”)
✗
1[b]/[h]
A hierarchy of ≥2 levels of computing planes
One compute level (tiles); islands/columns are interconnect groupings, not planesGraphcore, Hot Chips 33
✗
Same patent, same construction, same seven limitations. Both products clear the generic elements; the case turns entirely on [1f–g] — Corsair has a true grid-of-grids of complete planes; Graphcore’s grouping is interconnect wiring, not nested processors. A precise, checkable distinction — not an asserted verdict.
The honest read
What to diligence.
The clean core
US 9,075,768 and US 8,811,387 carry literal or near-literal reads on narrow, defensible claims. This is the part of the portfolio that holds up under scrutiny — and where the litigation value sits.
The broad net
US 10,565,036 reaches the whole industry because it covers the dispatch every GPU performs — which is also what makes it the most exposed to a validity challenge. Treat its breadth as licensing leverage, not a litigation spearhead.
Narrowed claims
The five narrowed patents read on most — but not every — element of a claim; one element is contested on each. Useful pressure in negotiation; confirm that element before relying on it.
Standing
A confirmatory assignment and a release of an older security interest should be recorded to put title beyond dispute before filing.
